1. Technical Field
The present invention relates to circuit design verification in general, and, in particular, to computer software for analyzing the functional correctness of a circuit design.
Still more particularly, the present invention relates to a method and apparatus for performing temporal checking.
2. Description of Related Art
Design verification is typically utilized to determine whether a device exactly implements the requirements defined by the specification of that device. Design verification for a device under testing (DUT) may be performed on an actual device, or, most likely, on a simulation model of the device.
The process of verifying a design through a simulation model of a DUT is aided by the availability of hardware description languages (HDLs) such as Verilog and VHDL. In order to interface with the simulation model of the DUT described in HDLs, a verification engineer typically has to write additional programming code for the purpose of performing design verification on the DUT. The resultant simulated model of the DUT can receive input stimuli in the form of test vectors. The results produced by the simulated model of the DUT are then checked against the expected results for the DUT.
Testing environments can be static or dynamic. A static testing environment drives pre-computed test vectors into the simulation model of a DUT and examines the results after the operation. However, if a static testing environment is used to examine the results that are output from the simulation model of a DUT, then errors in the test are not detected until after the test has been completed. As a result, the internal state of the DUT at the point of error may not be determinable, requiring the simulation to be repeated again in order to determine such internal states. Thus, static testing may require the expenditure of considerable time, especially during long tests.
Dynamic testing environments are more useful and efficient. In a dynamic testing environment, a set of programming instructions is written to generate the test vectors in concurrence with the simulation model of a DUT while potentially being controlled by the state feedback of the simulated model of the DUT. Dynamic testing enables directed random generation to be performed, and is more sensitive to effects uncovered during the test itself on the state of the simulation model of the DUT. Thus, dynamic testing clearly has many advantages for design verification over static testing.
However, both static and dynamic testings can be implemented only with fixed-vector or pre-generation input. A more sophisticated functional verification system enables a test generation to produce the environment, particularly for functional verification in order for various elements to be defined and connected together correctly so that a DUT can perform as specified. An example of such functional verification system is the SpecmanJ tools developed by Verisity Ltd. in Israel and available through Verisity Design, Inc. in Mountain View, Calif.
For functional verification of state-of-the-art integrated circuit devices, it is essential to use an efficient methodology to check the dynamic behavior of various signals and/or buses. Such kind of functional verification is commonly referred to as temporal checking. Temporal checking can be as simple as checking for a single pulse of a certain minimum or maximum length, or can be as complex as verifying complicated sequences of events in a bus protocol.
The common implementation of temporal checking via a cycle-based HDL simulator is to use a software simulation interface, such as the SpecmanJ tools, that is able to read the signals of interest in each simulation cycle. During testing, the software simulation interface monitors the testing by interrupting and querying the cycle-based HDL simulator on every clock edge in order to obtain the state and value of the signal(s) of interest. The cycle-based HDL simulator has to be re-started after each querying is done. Because of the cycle-based HDL simulator has to be constantly interrupted and re-started during temporal checking, the simulation speed is significantly reduced. In addition, the ratio of runtime state to interrupted state is relatively low because the cycle-based HDL simulator may only be allowed to run for very short periods of time (as small as one clock cycle) before each interruption. Those drawbacks become a performance bottleneck when verifying a very-large integrated circuit design where many thousand signals need to be checked simultaneously.
Consequently, it would be desirable to provide an improved method for performing temporal checking.